Chip Industry Technical Paper Roundup: Oct. 27
Chip Industry Technical Paper Roundup: Oct. 27
Semiconductor Engineering added several semiconductor technical papers covering imec's 3D DRAM-on-GPU thermal design, TU Munich's multilayer CFET self-heating and parasitic effects, 200G/λ silicon photonics modulators, dry-deposited resists for e-beam and EUV lithography, plus neural network SPICE modeling at 3nm, security-aware mapping for 3D CiM accelerators, and Pt-W absorber evaluation for high-NA EUV masks.
3D DRAM-on-GPU thermal design; multi-tier CFET self-heating and parasitics; 200G/λ silicon photonics; dry-deposited EUV and e-beam resists; neural-network-based SPICE modeling for 3nm; security-aware 3D CiM mapping; Pt-W absorbers for high-NA EUV masks.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Beyond HBM-on-GPU: Thermal Design Envelope for 3D Volumetric DRAM-on-GPU Integration | imec |
| Self-Heating and Parasitic Effects in Multi-Tier CFET Design | TU Munich, IIT Kanpur |
| Reduced-DSP 200G/λ Low-Voltage Slow-Light Silicon Modulator Enabled by Built-In EO Equalizer | Institute of Science Tokyo, Yokohama National University, AIST, PETRA |
| Irradiation-Source-Dependent Tone Conversion in Dry-Deposited Halogenated Amorphous Zeolitic Imidazolate Framework Resists for Electron-Beam and EUV Lithography | KU Leuven, Kunsan National University, Vrije Universiteit Brussel, imec |
| NN-Based Transistor Modeling for Ultra-Fast SPICE Simulation and Standard Cell Library Characterization | TU Munich |
| SEAL: Multitenant Security-Aware Layer Mapping for Heterogeneous 3-D CiM Accelerators | Arizona State University, University of Maryland |
| Evaluating an alternative Pt-W alloy as a low-n EUV mask absorber: Film properties and imaging performance | Chinese Academy of Sciences et al. |
Find more semiconductor research papers here.
Linda Christensen
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Linda Christensen is vice president of operations and a contributing writer at Semiconductor Engineering.
Source: Semiconductor Engineering Chips and Packaging · semiengineering.com