Nanoelectromechanical Switches Target More Efficient Embedded DRAM (UC Berkeley, Samsung, Intel)

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Researchers from UC Berkeley, Samsung, and Intel published a paper in an IEEE journal proposing a nanoelectromechanical gated gain cell embedded DRAM. Slowing SRAM scaling and the memory wall have renewed interest in gain cell eDRAM, but the approach still faces challenges including limited retention time, parasitic coupling, and the need for higher write voltage.

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Researchers at the UC Berkeley, Samsung Electronics, and Intel published “Nanoelectromechanically Gated Gain Cell eDRAM.”

Abstract Excerpt:
“The memory wall and the slowdown of static random access memory (SRAM) scaling have renewed interest in gain-cell embedded dynamic random access memory (DRAM). While gain cells offer high density and energy efficiency, they suffer from limited retention, parasitic coupling, and the need for boosted write voltages. This work introduces a nanoelectromechanically gated gain cell for embedded DRAM. ”

Find the technical paper here. October 2026

Finnan, Collin P., Choong-Ho Rhee, Tahir Ghani, and Tsu-Jae King-Liu. “Nanoelectromechanically Gated Gain Cell eDRAM.” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (2026): 223–230. https://doi.org/10.1109/JXCDC.2026.3717204. Open Access license.