UC Berkeley et al. Propose Nanoelectromechanical-Gated eDRAM
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On October 19, 2026, Semiconductor Engineering reported that researchers from UC Berkeley, Samsung Electronics, and Intel jointly published a paper in an IEEE journal proposing a nanoelectromechanical-gated gain-cell embedded DRAM. According to the report, the scheme was proposed as gain-cell eDRAM regains industry attention amid slowing SRAM scaling and an increasingly prominent memory wall problem. However, the report also notes that the scheme still faces several challenges, including limited retention time, parasitic coupling issues, and the need for higher write voltage. The above is all the reported content currently available; no further developments have followed.
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- Semiconductor Engineering Chips and PackagingNanoelectromechanical Switches Target More Efficient Embedded DRAM (UC Berkeley, Samsung, Intel)
Researchers from UC Berkeley, Samsung, and Intel published a paper in an IEEE journal proposing a nanoelectromechanical gated gain cell embedded DRAM. Slowing SRAM scaling and the memory wall have renewed interest in gain cell eDRAM, but the approach still faces challenges including limited retention time, parasitic coupling, and the need for higher write voltage.
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