What Breaks When Packaging Moves From Wafer To Panel?

Key Takeaways:

• Moving advanced packaging from wafer to panel changes more than available area. Processes developed around wafer geometry, handling, and equipment have to be reconsidered at panel scale.
• Larger panels amplify dimensional change, warpage, and process history, making what happens at one manufacturing step increasingly important to the next.
• The most economical manufacturing flow may use different substrate formats at different stages rather than carrying one large panel through the entire process.

Moving advanced packaging from wafer to panel sounds, at first, like a geometry problem. Large AI and HPC packages are increasingly rectangular, while the 300mm wafer underneath them is still round. As the package size grows, more of that expensive processing ends up around the circle’s edges where nothing useful can be built.

A panel gives that area back. It can fit more large packages into the same process cycle, and unlike a wafer, its dimensions don’t impose the same hard limit on the size of a square or rectangular package. For advanced packages that keep getting larger, the economics are difficult to ignore.

But the semiconductor packaging sector has spent decades learning how to process wafers, not panels. Equipment, materials, recipes, handling systems, and process controls were all developed around the geometry and mechanical behavior of a round workpiece.

“The risk of doing the assembly on the 600mm panel is high, and I don’t think we have all the equipment today to run the process,” said Teck Chong Lee, technical director of advanced fan-out development for HPC applications at ASE, in a recent presentation. “One of the options is, once you complete the interposer in large format in 600, then you divide it into four pieces to run the assembly and the C4 process. This is a much lower-risk approach.”

The economics behind that compromise are substantial. In the same study, a 5.5×-reticle-size interposer produced 9 units on a 300mm wafer, compared with 16 on a 300mm panel. A 600mm panel divided into four 300mm pieces produces 64, while processing the full 600mm area intact raises that to 72. In pure utilization, the intact panel produces 8 times as many units as the wafer, a gain well beyond the roughly fivefold difference in raw area, because the rectangular panel wastes almost nothing at its edges.

The flow therefore takes the area advantage where it can use it, then gives some of it back before assembly because the manufacturing infrastructure isn’t ready to follow the larger format all the way through. That compromise exposes the larger transition underway. Moving packaging from wafer to panel isn’t simply making the process bigger. It is discovering which parts of the process were dependent on the wafer dimensions all along.

The process was built around the wafer
The utilization advantage grows as the package does. In one comparison, Intel Foundry used a 510 × 515mm panel and showed that a roughly 4× reticle package would produce about 10 units on a 300mm wafer and approximately 48 on the panel. Eventually the wafer imposes a harder geometric limit, since the largest square that fits on a 300mm wafer is only about 210 × 210mm.

“For certain form factors, we believe a wafer is more economical,” said Tarik Ibrahim, senior principal engineer at Intel, in a conference presentation. “However, when you go beyond a certain form factor, you can see quickly that the panel becomes more effective, mainly because you can get more units out of a panel. Because of the way AI is heading and the need for a very large system, panels became an obvious choice for scale.”

Fig. 1: Intel’s Tarik Ibrahim discusses substrate scaling for heterogeneous integration. Source: Semiconductor Engineering

The economic crossover doesn’t mean the manufacturing process crosses over with it. Much of the equipment and process knowledge used in advanced packaging was developed for a round wafer, and changing the shape and scale of the substrate changes what those processes have to do. Over time, many of those wafer-specific assumptions became invisible because the workpiece underneath them rarely changed. What looked like a requirement of the process was often just a requirement of the wafer.

“At wafer level, it’s a single-sided process,” Ibrahim said. “On panel, it’s actually a dual-sided process. Managing the process at that panel scale with the right uniformity and the right Cpk [process capability index] is definitely a challenge.”

Part of the challenge is that familiar wafer processes don’t always transfer cleanly to a larger rectangular surface. Spin coating, for example, relies on radial symmetry, so a rectangular substrate produces uneven film thickness toward the corners while most of the dispensed resist is thrown away. In a 600mm panel flow, photoresist is instead deposited by slit or slot-die coating across an active area of roughly 586 × 586mm. Lithography also changes, with maskless direct imaging displacing the conventional wafer stepper in many panel flows.

Those differences propagate into the materials and equipment surrounding the process. Fine-line RDL on glass panels is pushing toward new photoresists and application methods, tighter overlay control, and equipment that can maintain temperature and process uniformity across a much larger area. Large hot plates become a development problem of their own. As line and space moves from roughly 5µm toward 2µm and below, processes that historically belonged farther back in the packaging flow begin demanding something closer to front-end precision.

The awkward part is that the panel can’t simply inherit the front-end equipment built to provide that precision. Much of that infrastructure assumes a round 300mm wafer, while traditional substrate equipment was designed around different feature sizes and process tolerances. Panel-level packaging is landing somewhere between the two.

The result is less a scaled-up wafer flow than a new manufacturing process being assembled from pieces of several older ones. The panel solves an increasingly expensive geometry problem, but it also exposes how many coating, exposure, handling, and uniformity assumptions were tied to the wafer that came before it.

Yield decides how big is useful
The simplest argument for a larger panel is that more packages fit on it. The real economic question is how many good packages come off.

That matters more as the value assembled onto the workpiece rises. A panel carrying logic and HBM can contain tens of thousands of dollars of known-good silicon before some package-level failures become visible. At that point, even a small yield loss can erase the savings created by processing more area at once.

“There’s so much money in chips going onto a wafer or panel that a tiny yield hit, and the loss of some of that super-expensive silicon, will just blow all the benefits from a larger scale that you had right out the window,” said Mike Kelly, vice president of chiplets and FCBGA integration at Amkor. “Defects are going to happen. It’s not defect-free, so you’ve got to have a great way to repair and not suffer yield loss. Otherwise, you’ve lost the whole benefit of getting large.”

That makes rework capability a design requirement, instead of a contingency. A panel that cannot be repaired converts every localized defect into a loss proportional to how much value the panel is carrying, which is precisely the value the larger format was adopted to accumulate.

ASE’s numbers show the tradeoff directly. Preserving the extra 12.5% of usable area that comes with keeping the 600mm panel intact also carries the process into the format that Lee describes as more difficult to control and not yet supported by all the necessary assembly equipment.

The largest manufacturable panel therefore may not be the most economical one. More area makes each process cycle more productive, but it also puts more value at risk when something goes wrong. The practical limit is set by yield as much as geometry.

The panel carries its history forward
Yield at the panel scale depends on more than defect density. It also depends on how predictably the panel behaves as it moves through the flow, because every operation leaves it slightly different for the next one.

Materials are heated, cured, deposited, plated, and cleaned as the package advances. Dimensions can shift, stress can build, and material properties can change with temperature and processing. What arrives at the next tool therefore isn’t quite the same structure that arrived at the one before it.

It therefore makes sense to take measurements when the package changes state. But those state changes become harder to manage as the workpiece gets larger. At wafer scale, decades of manufacturing experience have established how much movement particular processes tend to create and how much the next operation can tolerate. A panel adds a much larger area across which those changes have to remain predictable and uniform, often using materials and process combinations with far less production history.

Glass can reduce part of that movement. In tests simulating the formation of two RDL layers, dimensional stability improved significantly as the substrate moved from standard high-Tg organic material to ultra-low-CTE material and then to glass.

“The standard high-Tg material showed an average shift of about 22 microns at three sigma,” said Lars Boettcher, group manager for substrate and panel technologies at Fraunhofer Institute for Reliability and Microintegration (IZM), in a conference presentation. “The ultra-low-CTE material was much better and more homogeneous, but still in the range of seven microns. With the glass core, it was very uniform and somewhere around three microns, although that may already be approaching the measurement accuracy of the machine we used.”

Better dimensional stability doesn’t mean the rest of the structure stops moving, however. Thermal processing can still change where dies end up, and on a large panel that movement may vary across the surface rather than behaving like a single offset that can be corrected in the next step.

“The glass carrier is rigid and could be CTE-matched to silicon or other structures on the package. It is very stable with a smooth surface, which allows for fine-pitch processing,” said Hamed Gholami Derami, business development engineer for packaging solutions at Brewer Science. “However, one of the limits of using glass could be the non-linear die shift during thermal processing, which makes it hard to correct for die shift, especially for large glass panels.”

That turns process history into an alignment problem. A die can be placed correctly early in the flow and still arrive somewhere else later because curing, deposition, or another thermal step changed the surrounding structure. The next layer has to be built on the panel that actually exists at that moment, not on the coordinates carried forward from the original design.

The same history complicates simulation. Mechanical properties such as Young’s modulus and shear modulus, which describe a material’s stiffness under tensile and shear loading, can change with temperature, and newer glass and polymer systems don’t always have the mature characterization data available for silicon. Generic properties can provide a starting point, but the model still has to estimate how much stress and warpage each process step will introduce before engineers commit material and equipment to an actual build.

“Before you fail your manufacturing or your yield, do simulation. Don’t speculate,” said Lang Lin, product management principal at Synopsys. “Do a simulation with general properties and general processes and see how much warpage and stress each process creates, and then start your experiment.”

The limitation is that a generic model can only go so far. Accurate prediction eventually depends on the behavior of the actual materials in the stack, including how those properties change with temperature and processing. Some of the best data for doing that also may be proprietary. A material or substrate supplier can provide enough characterization data to improve the model without necessarily revealing the formulation or manufacturing details that produced it.

That leaves panel manufacturing as much a feedback problem as a modeling problem. Each process changes the physical structure that the next process receives, while measurements and models must keep catching up with those changes. The larger the panel becomes, the more expensive it is to discover late in the flow that one of those earlier assumptions was wrong.

Dicing the panel creates another problem
ASE’s mixed-format flow manages that risk by creating a new boundary in the process, but it only works if the 600mm glass panel can survive becoming four smaller ones.

“You have to design the layout of the 600mm panel from the start around how it will eventually be separated into four 300mm panels,” said ASE’s Lee. “It’s not a single dicing process. It involves several steps, plus some edge processing to remove the sharp edge.”

That makes the cut an upstream design constraint. The panel layout has to anticipate where the eventual separation will occur, while the dicing process must avoid leaving chips or damaged edges that can turn into breakage during the assembly steps that follow. ASE found that simply cutting the panel wasn’t enough. The separation process required multiple operations followed by edge treatment before the smaller panels could continue through the flow.

The cut edge isn’t the only place glass can carry damage forward. Through-glass vias introduce another stress concentration inside the material, because copper and glass expand at different rates as temperature changes. During heating, the copper expands more rapidly and protrudes, concentrating compressive stress in the surrounding glass. As the structure cools, the copper contracts and pulls on the glass sidewall, creating tensile stress that can drive a circumferential crack into the surrounding material. Finding those cracks introduces its own process-control problem.

“There is no standardization in the industry today,” said Poulomi Mukherjee, process integration engineer for advanced packaging at Applied Materials, in a conference presentation. “We need to figure out what would be the correct thermal testing, because finding the glass cracks is not that easy. So there’s a lot of metrology there, as well.”

That pushes inspection upstream for much the same reason dicing moved upstream. A panel can survive one operation while carrying edge damage or an internal crack that becomes consequential only after another thermal cycle, handling step, or assembly operation. By the time the failure becomes obvious, substantially more value may already have been added to the panel.

Some of the necessary controls do not exist yet. Important defects can be buried inside interconnects, while unfamiliar combinations of materials create correlations manufacturers are still learning how to recognize. A recipe can also work in a controlled demonstration and then encounter variation once it begins moving across lots and multiple tools.

“When it became mass production, there was still a learning curve to be done,” said Tiago Tavares, program and project manager at Critical Manufacturing. “You have to implement the controls ahead, and some of the controls you need to invent because they are not yet there.”

The larger economic argument for panel processing therefore depends on more than getting additional packages onto a larger workpiece. The process also has to find damage early enough that the additional area doesn’t simply create more expensive material to lose.

Conclusion
The usual picture of panel-level packaging assumes the industry eventually settles on a standard large format and builds an equipment ecosystem around it, much as semiconductor manufacturing converged on 300mm wafers.

ASE’s mixed-format approach suggests the transition may be less tidy. A 600mm panel can be the right answer when utilization dominates the economics, but not the right answer later, when yield, handling, or equipment availability become more important. Cutting it down sacrifices some area efficiency but returns the workpiece to a manufacturing environment that is easier to control.

Different parts of the flow may arrive at different answers. Coating and RDL benefit from the larger area, while assembly may favor a smaller format. Dicing has to anticipate what comes afterward. Inspection has to find damage before more value is added. Repair has to be possible once it does. And the accumulated thermal and mechanical history of the panel can change what the next tool is actually being asked to process.

For years, the wafer made many of those choices invisible because the equipment, materials, and process assumptions had already converged around it. Panel-level packaging is forcing engineers to make them explicit again. The industry may eventually standardize the panel, but first it has to separate what belongs to the process from what only looked like it did because there was always a wafer underneath it.

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