Self-Heating And Parasitics Challenge Multi-Tier CFET Scaling (TU Munich, IIT Kanpur)

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Researchers from TU Munich and IIT Kanpur published a paper in an IEEE journal using experimentally calibrated TCAD models to study self-heating effects and MOL/BEOL parasitics in multi-tier CFET designs, comparing a four-tier stacked nanosheet CFET against a conventional two-tier scheme.

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Researchers at the Technical University of Munich and Indian Institute of Technology Kanpur published “Self-Heating and Parasitic Effects in Multi-Tier CFET Design.”

Abstract Excerpt:
“We study the impact of self-heating effects (SHEs) and middle of line (MOL) and back-end of line (BEOL) induced parasitics on multi-tier CFET design, where multiple nanosheet devices are vertically stacked. We analyze and compare the four-tier complementary FET (CFET) design with the conventional two-tier CFET, using TCAD models calibrated to experimental measurements. In addition, TCAD simulations are used to model and analyze SHE-induced heat distribution and temperature profiles and to extract the detailed parasitic RC network from 3-D models of CMOS inverters designed with full MOL and BEOL interconnects.”

Find the technical paper here. June 2026

Shahin, Sufia, Mahdi Benkhelifa, Yogesh Singh Chauhan, and Hussam Amrouch. “Self-Heating and Parasitic Effects in Multi-Tier CFET Design.” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 12 (2026): 153–158. https://doi.org/10.1109/JXCDC.2026.3704373. License.