TU Munich and IIT Kanpur study self-heating and parasitic effects in multi-tier CFETs
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Researchers from TU Munich and IIT Kanpur published a paper in an IEEE journal, using experimentally calibrated TCAD models to study the impact of self-heating effects and MOL/BEOL parasitic parameters on multi-tier CFET (complementary field-effect transistor) designs. The study compared a four-tier stacked nanosheet CFET design with a conventional two-tier design, showing that self-heating effects and parasitic parameters are limiting factors for scaling multi-tier CFETs. This is currently the only report on the event, with no follow-up developments.
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- Semiconductor Engineering Chips and PackagingSelf-Heating And Parasitics Challenge Multi-Tier CFET Scaling (TU Munich, IIT Kanpur)
Researchers from TU Munich and IIT Kanpur published a paper in an IEEE journal using experimentally calibrated TCAD models to study self-heating effects and MOL/BEOL parasitics in multi-tier CFET designs, comparing a four-tier stacked nanosheet CFET against a conventional two-tier scheme.
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