Siemens EDA Releases Calibre DE-Via Tool
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On October 19, 2026, Semiconductor Engineering reported that Siemens launched the Calibre DesignEnhancer Via (DE-Via) tool. The tool addresses via resistance, electromigration, and routing density issues in physical design by automatically inserting redundant vias, while ensuring DRC-clean layouts after modifications. DE-Via adopts a shift-left approach, improving via robustness early in the design phase and reducing the number of iterations during the later signoff stage. In addition, the tool can identify areas prone to shorts and avoid inserting vias in those areas to maintain manufacturing efficiency while keeping the issues visible. Only this one report has been seen so far, and the event is in its initial stage.
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- Semiconductor Engineering Chips and PackagingShift-Left DE-Via
Siemens' Calibre DesignEnhancer Via (DE-Via) addresses via resistance, electromigration, and routing density issues in physical design by automatically inserting redundant vias, while ensuring layout modifications remain DRC-clean. This shift-left approach improves via robustness early in design, reducing late signoff iterations, and identifies areas prone to shorts while avoiding insertion there to preserve productivity and issue visibility.
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