SEAL Framework Reduces Fault Vulnerability of 3D Compute-in-Memory Accelerators
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On October 26, 2026, Semiconductor Engineering reported that researchers from Arizona State University and the University of Maryland published the SEAL framework. The framework targets heterogeneous 3D compute-in-memory (CiM) accelerators, jointly optimizing power, performance, area, and fault vulnerability by assigning critical neural network layers to more fault-resilient device and layer combinations, thereby reducing the fault vulnerability of 3D CiM accelerators. The current report is limited to the proposal and methodology of the framework, with no further reports of applications or real-world deployment yet.
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- Semiconductor Engineering Chips and PackagingSecurity-Aware Layer Mapping Reduces Fault Vulnerability In 3D Compute-In-Memory (ASU, U. of Maryland)
Researchers at Arizona State University and the University of Maryland have published the SEAL framework for heterogeneous 3D compute-in-memory (CiM) accelerators, which jointly optimizes power, performance, area, and fault vulnerability by mapping critical neural network layers to more fault-resilient device and tier combinations.
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