Self-Aligned CFET Architecture May Support CMOS Scaling Below 10Å
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The Semiverse Solutions team conducted a study on the self-aligned CFET (complementary field-effect transistor) architecture, aiming to verify whether it can support CMOS scaling at nodes below 10 angstroms (Å). The team used a digital twin process modeling approach to validate the SA-CFET architecture. Architecturally, SA-CFET boosts transistor density by vertically stacking NMOS and PMOS, and introduces three self-aligned modules: SA-BPR (self-aligned buried power rail), SA-CT (self-aligned contact), and SA-TSV (self-aligned through-silicon via), to meet the process integration requirements of sub-10Å nodes. The latest update on this research comes from a report published in the Chips & Packaging section of Semiconductor Engineering on October 22, 2026, which presented the results of this digital twin modeling validation. Publicly available information indicates that this work is still at the process modeling and validation stage, with no reports of mass production or tape-out progress.
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- Semiconductor Engineering Chips and PackagingHow Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å
The Semiverse Solutions team used digital twin process modeling to validate a self-aligned CFET (SA-CFET) architecture that extends CMOS scaling at sub-10 Å nodes by vertically stacking NMOS and PMOS together with three self-aligned modules: SA-BPR, SA-CT, and SA-TSV.
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