Introduction to the FP8 Format (Part 1): Arm Explains E4M3/E5M2 Encoding and the FP8 Instruction Set

The FP8 low-precision floating-point format is gradually being adopted in AI computing. NVIDIA deployed FP8 in its Hopper H100 GPU, and major machine learning frameworks already support the format. Arm has incorporated FP8 into the Arm v9 ISA and supports FP8-related configurations through the FPMR register. To unify the format standard, Arm, Intel, and NVIDIA jointly released the OCP 8-bit floating-point specification (OFP8) as a common format for model exchange. FP8 includes two encoding schemes, E4M3 and E5M2, which make different trade-offs between precision and dynamic range, suited to different scenarios such as inference and training. This first article in the series has Arm explain the E4M3/E5M2 encoding principles, the role of the FPMR register, and the design of the FP8 instruction set in Arm v9, helping developers understand how FP8 is implemented at both the hardware and software levels. This is the first installment of a technical explainer series, with no follow-up progress reported yet.

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