Independent Testing Reveals Severe Missed Defects in Frontier Large Model Chip Verification
Understand the story
On November 2, 2026, Brian Bailey of Semiconductor Engineering published a commentary arguing that EDA startups generally overstate AI's capabilities in chip verification and lack fair means of proof. The article cites the results of an AI blind test on chip verification: Claude Opus 5 missed roughly 168 of the defects deliberately planted in the test. Bailey uses this to show that, despite the heavy vendor marketing, frontier large models still exhibit clear missed-detection problems on chip verification tasks, and the industry also lacks fair third-party proof to test each vendor's claimed AI verification capabilities. So far, the commentary mainly presents the test results and criticism of industry marketing practices; no follow-up responses from vendors or the testers have been reported.
AI overview of reporting · Updated 2 h前
Reporting timeline
Explore different aspects of the story through its reporting.
- Semiconductor Engineering Chips and PackagingPutting AI To The Test
Semiconductor Engineering's Brian Bailey reviews how current EDA startups overstate AI verification capabilities and lack fair proof, in a blind test where Claude Opus 5 missed roughly 168 hand-planted defects.
Story heat trend
Not enough continuous observations to show a trend yet.