Intel Foundry Analyzes Power Delivery Challenges and Solutions for Stacked Multi-Chip Architectures
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Intel Foundry published an article analyzing power delivery technologies for stacked multi-chip architectures. While this architecture can improve the performance, bandwidth, and integration of AI and HPC systems, it brings a surge in current density and the number of independent voltage domains, causing power integrity challenges such as voltage droop and loss of guard bands. Intel Foundry's proposed solution is to move voltage regulation closer to the load, specifically including three technologies: FIVR based on CoaxMIL magnetic inductors, the all-capacitive C2VR regulator, and a flexibly placeable IVR chiplet architecture. These solutions aim to reduce power distribution losses, improve transient response, and support future multi-kiloamp load requirements.
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Intel Foundry notes that while stacked multi-chip architectures boost performance, bandwidth, and integration for AI and HPC systems, the surge in current density and the number of independent voltage domains brings power integrity challenges such as voltage droop and guard-band losses. Its solution is to move voltage regulation closer to the load, including FIVR based on CoaxMIL magnetic inductors, all-capacitive C2VR regulators, and a flexibly placeable IVR chiplet architecture, to cut power delivery losses, improve transient response, and support future multi-kiloamp loads.
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