TU Munich Uses Neural Networks to Accelerate 3nm SPICE Simulation
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Researchers at the Technical University of Munich have developed a neural network-based model for 3nm nanosheet transistors, for use in SPICE simulation and standard cell library characterization. Compared with the industry-standard Verilog-A implementation (BSIM-CMG), the NN model has errors below 0.11% and 0.76% in delay and total power evaluation respectively, while accurately predicting leakage current and various charges. In terms of performance, standard cell library characterization time is reduced by up to 8x. According to a report by Semiconductor Engineering on October 26, 2026, this work demonstrates the potential of neural network modeling for circuit simulation at advanced process nodes.
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- Semiconductor Engineering Chips and PackagingNeural Networks Speed 3nm Nanosheet SPICE Simulation (TU Munich)
Researchers at the Technical University of Munich have developed a neural network-based 3nm nanosheet transistor model for SPICE simulation and standard cell library characterization. Compared to the industry-standard Verilog-A implementation (BSIM-CMG), the NN model shows errors below 0.11% in delay and 0.76% in total power estimation, and cuts standard cell library characterization time by up to 8x while accurately predicting leakage current and various charges.
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