AI-Auto-Generated Verification Properties: Progress in Methodology Adoption
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On October 29, 2026, Semiconductor Engineering reported on a chip design industry analysis of methodologies for using AI to automatically generate verification properties from specifications. The report noted that AI can currently generate SystemVerilog assertions in seconds, demonstrating an advantage in generation speed; however, a key obstacle is that most existing chip design specifications are incomplete or ambiguously worded, making it difficult to use AI-generated properties directly. This indicates that the bottleneck for AI-generated verification properties lies not in the generation step itself, but in the quality of upstream specification documents. The methodology is still at the analysis and discussion stage, with no reports of large-scale adoption yet.
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- Semiconductor Engineering Chips and PackagingAuto-Generation Of Properties: Methodology Insertion
The chip design community discusses the current state of using AI to auto-generate properties from specifications: AI can generate SystemVerilog assertions in seconds, but most existing specifications are incomplete or vague, making generated results hard to use directly.
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