SPIE Expert Panel Discusses EPE and Computational Lithography
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At the SPIE Photomask and EUV Lithography conference, experts from IBM, Carl Zeiss SMT, Micron, ASML, Tekscend, and Applied Materials held a panel discussion focused on edge placement error (EPE) and next-generation computational lithography. The experts noted that EPE is no longer just a single lithography metric but has become a system-level issue, with contributions from mask, scanner, photoresist, etch, metrology, and OPC steps. The discussion centered on how to go beyond the traditional EPE budget framework and build next-generation computational lithography technology.
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- Semiconductor Engineering Chips and PackagingBeyond The EPE Budget: Building The Next Generation Of Computational Lithography
At the SPIE Photomask and EUV Lithography conference, a panel of experts from IBM, Carl Zeiss SMT, Micron, ASML, Tekscend and Applied Materials said edge placement error (EPE) has risen from a single lithography metric to a system-level problem, with contributions from masks, scanners, photoresist, etch, metrology and OPC.
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