AI Edge Inference Drives Memory Architecture Restructuring

As large language models move from data centers to edge devices and physical AI, the industry is rethinking memory architecture. Under the traditional von Neumann architecture, data is frequently shuttled between memory and compute units, resulting in high power consumption and latency that struggle to meet edge inference needs. To address this, the industry is exploring technologies such as PNM (processing near memory) and PIM (processing in memory), bringing computation closer to memory or even inside it, to reduce data movement, lower power consumption, and improve inference efficiency. According to a Semiconductor Engineering report on November 12, 2026, rethinking memory architectures for AI inference is becoming an important direction in the chip and packaging field. This event is currently mainly reflected in discussions of technical directions and restructuring trends; the report gives no specific product launches or commercialization timelines.

AI overview of reporting · Updated 2 h前

Not enough continuous observations to show a trend yet.