Semiconductor Engineering Blog Roundup: Chiplets, Rack-Scale Design, and AI Data Centers

Semiconductor Engineering has continued to publish multiple blog posts on Chiplets, rack-scale design, and AI data center topics, with the event expanding over time. In the latest edition (November 4, 2026), Cadence announced a new physical AI subproject workflow built on the OCP Foundation Chiplet System Architecture to cover real-time safety-critical systems. In the same edition, several companies shared their views on related areas: Synopsys discussed rack-scale power and thermal issues, Siemens addressed how to tackle verification complexity, Arm introduced SME2 sparse matrix instructions, Keysight focused on liquid cooling for AI data centers, and SEMI provided a wafer shipment forecast. This series of reports presents a complete technical picture spanning from the chip level (Chiplets, verification, instruction set extensions) to the system level (rack power and cooling, liquid cooling) and to the industry level (wafer shipments), reflecting the industry's continued focus on interconnect, thermal, and manufacturing capabilities driven by AI compute.

AI overview of reporting · Updated 1 h前

Not enough continuous observations to show a trend yet.