AI Workloads Evolve Rapidly, Chip Testing Struggles to Keep Up
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According to a Semiconductor Engineering report on November 10, 2026, AI models and applications iterate faster than chip design, manufacturing, and testing cycles, forcing chipmakers to rethink test strategies. Multi-die packaging introduces more test insertion points and massive volumes of test data, which are scattered between fabs and OSATs and difficult to share. Single dies must handle power consumption of up to 3 kilowatts, and panel-level interconnect substrates are shifting to 310 × 310mm. In addition, manufacturers need to monitor chip aging and reliability, but test targets are hard to define as workloads change rapidly. This report is currently the only source of information on the matter, with no follow-up developments reported.
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- Semiconductor Engineering Chips and PackagingTest Struggles To Keep Pace With AI
AI models and applications iterate faster than chip design, manufacturing, and test cycles, forcing chipmakers to rethink test strategies. Multi-die packaging brings more test insertion points and massive data that is scattered across fabs and OSATs and hard to share; a single die must handle 3 kilowatts of power, and panel-level interconnect substrates are moving to 310 × 310mm. Makers must also monitor aging and reliability, while test targets are hard to pin down as workloads change rapidly.
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